1. Field of the Invention
The present invention relates to a liquid crystal apparatus and to a manufacturing method therefor. More particularly, the present invention relates to an in-plane switching liquid crystal display apparatus and to a manufacturing method therefor.
2. Description of the Related Art
In an active matrix liquid crystal display apparatus, an IPS (In Plane Switching) method, according to which the direction of an electric field to be applied to liquid crystals is set to be parallel to a substrate, is used mainly as a technique for obtaining an ultrawide viewing angle (see JP-A-8-254712). It has been revealed that the employment of this method almost eliminates change in contrast and inversion of a gradation level, both of which would occur when a viewing angle direction is changed (see M. Oh-e, et al.: Asia Display 95, pp. 577-580). FIG. 11A is a plan view showing a pixel portion of a conventional ordinary IPS liquid crystal display apparatus. Further, FIG. 11B is an enlarged view showing a part thereof. In these figures, reference numeral 100 designates a TFT array substrate, and numeral 200 denotes a color filer (CF) substrate. Further, numeral 1 designates a gate wiring that is a plurality of scanning-signal lines formed on an insulating substrate, numeral 2 denotes a gate insulating film, numeral 3 designates a source wiring, numeral 4 denotes an insulating film provided on the source wiring 3, and reference characters 5a and 5b designate common electrodes provided on a same layer as the gate wiring. Reference numeral 6 a pixel electrode disposed opposite to the common electrode. Especially, in this example, a common electrode 5 is placed by being split into the common electrode 5a and the common electrode 5b. Thus, in a sate in which a voltage is applied to the source wiring, an electric field E is generated due to the voltage and changes the orientation condition of liquid crystals provided between the TFT array substrate 100 and the CF substrate 200. Consequently, the portion of the configuration shown in FIGS. 11A and 11B needs a large width indicated by “L1” in the figure, so that the transmission of light therethrough is restricted. Therefore, this apparatus has a problem that the aperture rate thereof is low.
To solve such a problem, a structure shown in FIGS. 12A and 12B has been proposed. In this structure, a common electrode 5 covers a source wiring 3. Both the common electrode 5 and the source wiring 3 are disposed in such a way as to overlap with each other. With such a structure, an electric field generated from the source wiring 3 is shielded by the common electrode 5. Thus, the electric field does not reach the liquid crystal, so that the change in the orientation condition of the liquid crystal can be reduced. Consequently, the width L2 for restricting the transmission of light can be narrowed. The aperture rate can be enhanced.
In such an IPS liquid crystal display apparatus, an electric potential is generated in a direction being horizontal to the substrate due to a common electric potential Vcom at the common electrode 5 and an electric potential Vs at the pixel electrode 6, as shown in FIG. 13. A desired image is displayed by driving the liquid crystals in the direction being horizontal to the substrate.
Usually, an active matrix liquid crystal display apparatus is employed as the IPS liquid crystal display apparatus. In the active matrix liquid crystal display apparatus, pixels shown in FIGS. 12A and 12B are disposed in a matrix manner. Therefore, plural gate wirings 1 and plural source wirings 3 are placed therein. Further, a TFT, which is a switching device, is disposed in the vicinity of each of intersections between the gate wirings 1 and the source wirings 3.
Scanning signals are supplied to each of the gate wirings in Such a way as to switch between ON/OFF modes of the TFT connected thereto. On the other hand, display signals for driving the liquid crystals are supplied to the source wirings. In a time period during which this TFT is turned on, the source wiring 3 and the pixel electrode are conducted to one another, so that a display signal is written to the pixel electrode. The common electrode disposed opposite to the pixel electrode is supplied with common electric potential. The liquid crystals are driven by a driving voltage generated between the pixel electrode and the common electrode according to this display signal. Among the plural gate wirings, the gate wirings, the TFT connected to each of which is turned on, are sequentially scanned from an end one thereof. Then, the display signals are sequentially supplied to the plural source wirings 3 in synchronization with the scanning of the gate wirings, the TFT of each of which is turned on. That is, display signals for the pixels are written thereto in a period during which the associated TFT is turned on.
A period of turning-on of TFTs connected to all the gate wirings is called a vertical period. Generally, the frequency in the vertical period is 60 Hz. That is, in a time period of ( 1/60) sec., the gate wirings are sequentially scanned from the Lop one to the bottom one thereof, so that the display signals are written to all the pixel electrodes. Therefore, the rewriting of the screen is performed 60 times per second. Furthermore, a period of turning-on of each of TFTs connected to the gate wirings is called a horizontal period. The frequency in the horizontal period is given by multiplying (the frequency of the vertical period) by (the number of the gate wirings). Therefore, generally, a write time assigned to one gate wiring 1 is given by dividing ( 1/60 sec.) by (the number of the gate wirings).
Next, the scanning signal inputted to the gate wiring, and the display signal inputted to the source wiring 3 are described by using FIG. 14. FIG. 14 is a timing chart schematically showing the scanning signal inputted to the gate wiring, and the display signal inputted to the source wiring. In FIG. 14, reference character G designates a scanning signal inputted to the gate wiring, while character S denotes a display signal inputted to the source wiring. Further, reference character Vcom designates a common potential supplied to the common electrode, while character Vs denotes a pixel potential supplied to the pixel electrode. FIG. 14 is drawn by focusing attention to a scanning signal for the single gate wiring 1 and to a display signal for the single source wiring.
As shown in FIG. 14, a positive gate pulse having a duration corresponding to one horizontal period (“1 H” shown in FIG. 14) is added to the scanning signal G. Consequently, the TFT is brought into an ON-state. In the horizontal period in which this TFT is in the ON-state, the level of the display signal S is at the pixel potential Vs corresponding to an associated pixel. This pixel potential Vs is written to the pixel electrode 6. The liquid crystals are driven by the electric field generated between the pixel electrode 6 and the common electrode 5. That is, the potential difference (Vs−Vcom) between the pixel potential Vs and the common potential Vcom is employed as a driving voltage.
Regarding the scanning signal G, in the next horizontal period, the TFT connected to the adjacent gate wiring 1 is turned on, so that a gate pulse is not added to the scanning signal G. That is, the scanning signal G is a signal adapted so that one gate pulse is added thereto in one vertical period. On the other hand, regarding the display signal S, in the next horizontal period, the level thereof is the pixel potential Vs to be written to the pixel electrode corresponding to the adjacent gate wiring. Therefore, the display signal S is a signal adapted so that the pixel potentials Vs of the plural pixel electrodes arranged in a line are sequentially set out as the levels thereof respectively associated with consecutive horizontal periods thereof.
The display signal, in which the pixel potentials Vs of the plural pixel electrodes arranged in a line are set out as such levels thereof, is supplied to the single source wiring 3. Thus, on the source wiring 3, even a pixel, the associated TFT of which is turned off, is supplied with the pixel potential Vs associated with another pixel placed on the same source wiring. This pixel potential Vs associated with the latter pixel causes the following problems.
As shown in FIGS. 12A and 12B, the source wiring 3 is disposed in the vicinity of the pixel electrode 6. In the case of the pixel, the associated TFT of which is turned off, the associated source wiring 3 and the associated pixel electrode 6 are at different potentials, respectively. For example, in a case where the adjacent pixels placed on the same source wiring respectively perform a white display and a black display, an electric potential causing a black display is applied to the pixel electrode 6, while an electric potential causing a white display is applied to the source wiring 3. Therefore, an error electric field differing from the electric field generated between the pixel electrode 6 and the common electrode 5 is generated between the pixel electrode 6 and the source wiring 3. The error field, which is generated between the pixels electrode 6 and the source wiring 3 at such writing of another pixel, affects a voltage applied to the liquid crystal and disturbs the orientation of the liquid crystals. Consequently, a problem has occurred, in which degradation in quality of display, such as a crosstalk, is caused.
As described above, the conventional. IPS liquid crystal apparatus has the problems that the error field generated between the pixel electrode 6 and the source wiring 3 at the writing of another pixel disturbs the orientation of the liquid crystals and causes defective display. To solve this problem, the width of the common electrode 5 shown in FIGS. 12A and 12B should be broadened. Thus, the conventional IPS liquid crystal apparatus has the problems that the aperture rate is restricted, that due to such restriction on the aperture rate, the aperture rate cannot be improved and the efficiency in using light is decreased.
Thus, the conventional IPS liquid crystal apparatus has the problems that the aperture rate is restricted by the error field between the pixel electrode 6 and the source wiring 3 at the writing of another pixel.